62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
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From 8374ca9a2f66ad1b36dbd4b53abba9c692fccee6 Mon Sep 17 00:00:00 2001
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From: Sajan Karumanchi <sajan.karumanchi@amd.com>
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Date: Tue, 3 Sep 2024 08:23:27 +0000
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Subject: [PATCH] backport-x86-Optimizing-memcpy-for-AMD-Zen-architecture
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Modifying the shareable cache '__x86_shared_cache_size', which is a
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factor in computing the non-temporal threshold parameter
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'__x86_shared_non_temporal_threshold' to optimize memcpy for AMD Zen
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architectures.
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In the existing implementation, the shareable cache is computed as 'L3
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per thread, L2 per core'. Recomputing this shareable cache as 'L3 per
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CCX(Core-Complex)' has brought in performance gains.
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As per the large bench variant results, this patch also addresses the
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regression problem on AMD Zen architectures.
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Origin backport: https://sourceware.org/git/?p=glibc.git;a=commit;h=8813b2682e4094e43b0cf1634e99619f1b8b2c62
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---
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sysdeps/x86/cacheinfo.c | 20 +++++++++++++++++---
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1 file changed, 17 insertions(+), 3 deletions(-)
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diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
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index 5b43fa78..37a03af0 100644
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--- a/sysdeps/x86/cacheinfo.c
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+++ b/sysdeps/x86/cacheinfo.c
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@@ -728,7 +728,7 @@ intel_bug_no_cache_info:
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threads = 1 << ((ecx >> 12) & 0x0f);
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}
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- if (threads == 0)
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+ if (threads == 0 || cpu_features->family >= 0x17)
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{
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/* If APIC ID width is not available, use logical
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processor count. */
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@@ -743,8 +743,22 @@ intel_bug_no_cache_info:
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if (threads > 0)
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shared /= threads;
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- /* Account for exclusive L2 and L3 caches. */
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- shared += core;
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+ /* Get shared cache per ccx for Zen architectures. */
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+ if (cpu_features->family >= 0x17)
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+ {
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+ unsigned int eax;
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+
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+ /* Get number of threads share the L3 cache in CCX. */
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+ __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
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+
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+ unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
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+ shared *= threads_per_ccx;
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+ }
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+ else
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+ {
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+ /* Account for exclusive L2 and L3 caches. */
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+ shared += core;
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+ }
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}
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#ifndef DISABLE_PREFETCHW
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--
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2.27.0
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