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x86:Add the virtual machine detection in init_cacheinfo

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Signed-off-by: May Shao <MayShao@zhaoxin.com>
This commit is contained in:
May Shao 2022-09-29 12:35:48 +08:00
parent 61af04844e
commit f98f66bd1d
2 changed files with 65 additions and 1 deletions
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6
glibc.spec
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@ -62,7 +62,7 @@
##############################################################################
Name: glibc
Version: 2.28
Release: 91
Release: 92
Summary: The GNU libc libraries
License: %{all_license}
URL: http://www.gnu.org/software/glibc/
@ -154,6 +154,7 @@ Patch67: sunrpc-Test-case-for-clnt_create-unix-buffer-overflo.patch
Patch68: CVE-2022-23218-Buffer-overflow-in-sunrpc-svcunix_cre.patch
Patch69: getcwd-Set-errno-to-ERANGE-for-size-1-CVE-2021-3999.patch
Patch70: x86-Fix-__wcsncmp_avx2-in-strcmp-avx2.S-BZ-28755.patch
Patch71: x86-Add-the-virtual-machine-detection-in-init_cacheinfo.patch
Provides: ldconfig rtld(GNU_HASH) bundled(gnulib)
@ -1213,6 +1214,9 @@ fi
%endif
%changelog
* Thu Sep 29 2022 May Shao <MayShao@zhaoxin.com> - 2.28-92
- x86: Add the virtual machine detection in init_cacheinfo
* Thu Jul 28 2022 Qingqing Li <liqingqing3@huawei.com> - 2.28-91
- optimize Obsoletes version

60
x86-Add-the-virtual-machine-detection-in-init_cacheinfo.patch Normal file
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@ -0,0 +1,60 @@
From 6d36c9b1273980cb8ff511f78b5c9b126e4577da Mon Sep 17 00:00:00 2001
From: May Shao <MayShao@zhaoxin.com>
Date: Tue, 27 Sep 2022 20:44:48 +0800
Subject: [PATCH 1/1] x86: Add the virtual machine detection in init_cacheinfo
Use CPUID.01H.ECX[31] to indicate guest status.
Set the default threads=1 to use non_temporal_threshold on
vm and hosts with a single processor.
Signed-off-by: May Shao <MayShao@zhaoxin.com>
---
sysdeps/x86/cacheinfo.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
index 7615334e..28bcf2f6 100644
--- a/sysdeps/x86/cacheinfo.c
+++ b/sysdeps/x86/cacheinfo.c
@@ -495,7 +495,8 @@ init_cacheinfo (void)
long int data = -1;
long int shared = -1;
unsigned int level;
- unsigned int threads = 0;
+ unsigned int threads = 1;
+ unsigned int is_vm = 0;
const struct cpu_features *cpu_features = __get_cpu_features ();
int max_cpuid = cpu_features->max_cpuid;
@@ -506,6 +507,9 @@ init_cacheinfo (void)
long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
bool inclusive_cache = true;
+ is_vm = ((cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx
+ & (1 << 31)) >> 31);
+
/* Try L3 first. */
level = 3;
shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
@@ -532,7 +536,7 @@ init_cacheinfo (void)
/* A value of 0 for the HTT bit indicates there is only a single
logical processor. */
- if (HAS_CPU_FEATURE (HTT))
+ if (HAS_CPU_FEATURE (HTT) && !is_vm)
{
/* Figure out the number of logical threads that share the
highest cache level. */
@@ -692,7 +696,7 @@ intel_bug_no_cache_info:
shared /= threads;
}
else
- threads = 1;
+ threads = 1;
/* Account for non-inclusive L2 and L3 caches. */
if (!inclusive_cache)
--
2.17.1